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Luis Tarazona
Correo/E-mail: luistarazona{at}unexpo{dot}edu{dot}ve

 Profesor Asociado a dedicación exclusiva adscrito al
Departamento de Ingeniería Electrónica.

Académico:  Asignaturas administradas (del 2000 al 2006)

Foto (Luis)

 

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Publicaciones recientes:

  • Luis Tarazona, Doug Edwards and Luis Plana. A Synthesisable quasi-delay insensitive result forwarding unit for an asynchronous Processor. Accepted to be published in: Proceedings of 12 Euromicro Conference on Digital System Design (DSD), August 2009.
  • Andrew Bardsley, Luis Tarazona and Doug Edwards. Teak: a token flow implementation for the Balsa language. Accepted to be published in: Proceedings of International Conference on Application of Concurrency to System Design (ACSD), July 2009.
  • L. A. Tarazona and D. A. Edwards. Performance-oriented peephole optimisation of Balsa dual-rail circuits. In Proceedings of the 20th UK Asynchronous Forum, September 2008.
  • Sam Taylor, Doug Edwards, Luis A. Plana and Luis A. Tarazona D. Asynchronous Data-Driven Circuit Synthesis. Accepted to be published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009.
  • L. A. Tarazona and D. A. Edwards. A result forwarding unit for a synthesisable asynchronous processor. In Proceedings of the 20th UK Asynchronous Forum, September 2008.
  • L. A. Plana, D. Edwards, S. Taylor, L. A. Tarazona, A. Bardsley, Performance-driven syntax-directed synthesis of asynchronous processors Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, pp. 43 - 47, Salzburg, Austria, ACM Press, September 2007 ISBN:978-1-59593-826-8 Abstract    DOI-Link
  • L. A. Tarazona, L.A. Plana, and D. A. Edwards, Architectural enhancements for a synthesised self-timed processor. Proceedings of the 19th UK Asynchronous Forum, London, UK, September 2007. Abstract    19th Async Forum Proceedings
  • L. A. Tarazona and D. A. Edwards, Automatic Buffer Insertion in Balsa-synthesised Asynchronous Circuits. Proceedings of the 19th UK Asynchronous Forum, London, UK, September 2007. Abstract    19th Async Forum Proceedings

Intereses:

  • Síntesis de Circuitos Asincrónicos
  • Procesamiento Digital de Señales
  • Diseño Digital